Various devices use voltages that are different from an input signal voltage. In such devices, the input signal voltage must be shifted to a high voltage or to a low voltage. A circuit that performs such shifting is known as a level shifter circuit.
FIG. 1 depicts a prior art level shifter circuit 10 comprising an input D adapted to receive a digital signal that is either at the level of an input power supply AVBB or an input ground AVSS. Assuming the input was AVSS (which would be logic low) then transistor M7 would be turned on. The P-channel devices, M6 and M8, are much weaker than the N-channel devices M5 and M7 so even if device M8 were initially on, when device M7 is turned on, it is strong enough to pull the output Q low thus overpowering device M8. As soon as the output Q goes low, device M5 is turned off because the input D is at a logical low level and device M6 is turned on which then pulls output QZ (inverse Q) high. There is no conflict at the output QZ because only device M6 is on. Therefore, the output is flipped such that Q is low and QZ is high. When the input D goes high, transistor M5 turns on and a fight between transistors M5 and M6 occurs because the output Q is, at this point, still low (transistor M6 is still turned on). Since the N-channel devices are stronger than the P-channel devices, M5 wins the fight between M6, the QZ output is pulled low, and device M8 is turned on which pulls the output Q high because at this point, device M7 is turned off.
One of the problems associated with the prior art level shifter circuit 10 is that because the P-channel devices have to be weak by design in order for the N-channel devices to be able to overpower them, when an output makes a transition from low to high, it is a slow transition because of a weak P-channel device above pulling it up. Conversely, when an output makes a transition from high to low, a strong N-channel device on the bottom is pulling it down. As such, a much faster high to low transition exists than a low to high transition which, in the case of a switching signal, is undesirable.
To overcome such a problem, the P-channel devices can be made stronger. However, the N-channel devices would then have to be made even stronger to ensure they win the fight between the P-channel devices and the circuit operates properly. Limitations exist, however, in that more power is used because even though a short period of time may elapse when an N-channel device and a P-channel device are fighting each other, current is shooting straight through from the input power supply to the ground until finally the other side flips and turns the P-channel device off. In order to save power, the devices can be made as weak as possible so that the shoot through current is minimized, however the speed of the circuit 10 would be comprised. The disparity between the output rise time and fall time would still exist so the propagation time between, for example, an input rising edge to an output rising edge would be relatively slow because of a weak P-channel device pulling the output high. In contrast, the delay time between an input falling edge to an output falling edge would be relatively fast because a strong N-channel device exists which pulls the output Q low. Such slow rise times and poorly matched rise and fall times are undesirable. For example, in a clocking signal, a 50% duty cycle clock waveform may exist but after the waveform passes through the circuit 10, excessive delay due to the slow nature of the circuit would exist. However, because the rising edge and the falling edge are delayed by a different amount, the 50% duty cycle clock waveform will be degraded.
Additional buffering may be used to overcome such limitations but, poor rise and fall time matching may still exist. The rise and fall times can be improved by adding inverter buffers to the output Q. This could improve the rise and fall time of the final signal but the delay is not improved because such a delay is present at the output Q. Adding additional buffering will not undo this delay once it is present at the output Q and may increase the cost and complexity of the circuit. Introducing delay is typically not recommended.
It is therefore desirable for the present invention to overcome the problems and limitations described above that are involved in a level shifter circuit.